Flash memory has become increasingly popular in recent years. A typical flash memory comprises a memory array having a large number of memory cells arranged in blocks. Each of the memory cells is fabricated as a field-effect transistor having a control-gate and a floating gate. The floating gate is capable of holding charges and is separated from source and drain regions contained in a substrate by a layer of thin oxide. Each of the memory cells can be electrically charged by injecting electrons from the drain region through the oxide layer onto the floating gate. The charges can be removed from the floating gate by tunneling the electrons to the source through the oxide layer during an erase operation. The data in a memory cell is thus determined by the presence or absence of a charge on the floating gate.
FIG. 1 illustrates two exemplary flash memory cells 2 and 20. Flash memory cell 2 includes a floating gate 4, a control-gate 6 over and electrically insulated from floating gate 4, and a word-line node 10 over a channel 12 and on sidewalls of floating gate 4 and control-gate 6. Wordline 10 controls the conduction of channel 12, which is between bit-line node 14 and source node 16. During a program operation, a voltage is applied between bit-line node 14 and source node 16, with, for example, a bit-line node voltage of about 0.4V and a source node voltage of about 5V. Wordline 10 is applied with a voltage of 1.1V to turn on channel 12. Therefore, a current (hence electrons) flows between bit-line node 14 and source node 16. A high voltage, for example, about 10V, is applied on control-gate 6, and thus the electrons are programmed into floating gate 4 under the influence of a high electrical field. During an erase operation, a high voltage, for example, 11V, is applied to an erase-gate 18. Word-line node 10 is applied with a low voltage such as 0V, while source node 16, bit-line node 14 and control-gate 6 are applied with a voltage of 0V. Electrons in floating gate 4 are thus driven into erase-gate 18.
Flash memory cells are placed as rows and columns to form flash memory arrays. FIG. 2 illustrates a conventional flash memory array formed of flash memory cells illustrated in FIG. 1, wherein flash memory cells 2 and 20 are shown as the cells in the first column. The remaining portions of the array are essentially repetitions of memory cells 2 and 20. In each row of the array, there is a global control-gate (CG) line, for example, global CG line 30 in the first row and global CG line 32 in the second row, used by all memory cells in the row. An erase-gate (EG) line 34 is shared by the first row and the second row. In an erase operation, a small portion of a row may need to be erased. However, due to the fact that all memory cells in a row share a common erase-gate, an entire row, and possibly an entire sector, which includes a plurality of rows, has to be erased. Those bytes not intended to be erased have to be written back after the undesirable erase. This not only causes an increase in the overall time for erase operations, but also in a reduction in the lifetime of the flash memory cells due to multiple undesirable program and erase operations. New methods to solve the above-discussed problems are thus needed.